Silicon Labs /Series1 /EFM32GG12B /EFM32GG12B810F1024IL112 /CMU /ADCCTRL

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Interpret as ADCCTRL

31282724232019161512118743000000000000000000000000000000000000000000 (NODIVISION)ADC0CLKDIV0 (DISABLED)ADC0CLKSEL0 (ADC0CLKINV)ADC0CLKINV0 (NODIVISION)ADC1CLKDIV0 (DISABLED)ADC1CLKSEL0 (ADC1CLKINV)ADC1CLKINV

ADC0CLKSEL=DISABLED, ADC0CLKDIV=NODIVISION, ADC1CLKSEL=DISABLED, ADC1CLKDIV=NODIVISION

Description

ADC Control Register

Fields

ADC0CLKDIV

ADC0 Clock Prescaler

0 (NODIVISION): undefined

ADC0CLKSEL

ADC0 Clock Select

0 (DISABLED): ADC0 is not clocked

1 (AUXHFRCO): AUXHFRCO is clocking ADC0

2 (HFXO): HFXO is clocking ADC0

3 (HFSRCCLK): HFSRCCLK is clocking ADC0

ADC0CLKINV

Invert Clock Selected By ADC0CLKSEL

ADC1CLKDIV

ADC1 Clock Prescaler

0 (NODIVISION): undefined

ADC1CLKSEL

ADC1 Clock Select

0 (DISABLED): ADC1 is not clocked

1 (AUXHFRCO): AUXHFRCO is clocking ADC1

2 (HFXO): HFXO is clocking ADC1

3 (HFSRCCLK): HFSRCCLK is clocking ADC1

ADC1CLKINV

Invert Clock Selected By ADC1CLKSEL

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